1. Field of the Invention
The present invention relates to an address transition detecting circuit for a semiconductor memory device, and more particularly to an improved address transition detecting circuit for a semiconductor memory device including a pulse generation circuit provided with a cross-coupled logic gate and a delay unit, capable of doubly generating a pulse signal which serves to activate a column address decoder circuit in accordance with an address transition detection signal.
2. Description of the Prior Art
As shown in FIG. 1, a conventional semiconductor memory device is provided with: an address transition detecting circuit 1 receiving a plurality of address signals A0.about.An outputted from an address buffer (not shown), detecting an address transition and accordingly outputting a second pulse signal (precharge signal) P, a first pulse signal (column address decoder enable signal) YE, and a third pulse signal (sense amplifier enable signal) SE using the combined signal; a column address decoder circuit 2 activated in accordance with the first pulse signal YE outputted from the address transition detecting circuit 1, decoding the address signals A0.about.An outputted from the address buffer (not shown), and outputting a plurality of control signals (column switching signals) S0.about.Sn, for selecting among a plurality of bit line pairs (BL0,/BL0).about.(BLn,/BLn); a column switch circuit 3 outputting data from a selected column of a memory cell array (not shown) in accordance with the bit line pairs (BL0,/BL0).about.(BLn,/BLn) selected by the control signals S0.about.Sn outputted from the column address decoder circuit 2; a precharger circuit 4 activated in accordance with the second pulse signal P outputted from the address transition detecting circuit 1, and supplying a charge to the data line pair DL,/DL connected to the column switch circuit 3; a sense amplifier circuit 5 activated in accordance with the third pulse signal SE outputted from the address transition detecting circuit 1, and sensing and amplifying a data signal applied thereto via the precharger circuit 4; and a data latch/output buffer circuit 6 for latching a data signal amplified in the sense amplifier 5 and generating an output signal DOUT.
With reference to FIG. 2, the address transition detecting circuit 1 includes: an address transition detecting sub-circuit 11 detecting transitions in address signals A0.about.An outputted from the external address buffer (not shown) to generate an address transition detection signal; an address transition detection summing circuit 12 summing the address transition detection signals outputted from the address transition sub-circuit 11; and a column controller 13 receiving an address transition detection sum signal ATDSUM outputted from the address transition detecting summing circuit 12, and outputting the first pulse signal YE for activating the column address decoder circuit 2 and the third pulse signal SE for activating the sense amplifier circuit 5.
The operation of the thusly constituted conventional memory device will now be described with reference to FIGS. 1 and 2.
When the address signals A0.about.An outputted from the address buffer (not shown) are transitted, the respective address transition detecting sub-circuit 11 of the address transition detecting circuit 1 and respectively generate address transition detection signals. The address transition detection summing circuit 12 serves to sum the address transition detection signals outputted from the address transition detection sub-circuit 11 for thereby outputting the summed signal ATDSUM.
The column controller 13 receives the address transition detection sum signal ATDSUM outputted from the address transition detection summing circuit 12, and outputs the first pulse signal YE for driving the column address decoder circuit 2, the second pulse signal P for driving the precharger circuit 4 and the third pulse signal SE for driving the sense amplifier circuit 5.
The column address decoder circuit 2 activated by the first pulse signal YE outputted from the column controller 13 decodes the address signals A0.about.An outputted from the address buffer (not shown) and outputs the control signals S0.about.Sn, and the column switch circuit 3 outputs data from a selected column of a memory cell array (not shown) to the data line pair DL,/DL in accordance with the bit line pairs (BL0,/BL0).about.(BLn,/BLn) selected by the control signals S0.about.Sn.
The precharger circuit 4 activated by the second pulse signal P outputted from the column controller 13 supplies electrical charge to the data line pair DL,/DL.
Then, when the second pulse signal P outputted from the column controller 13 is transitted, the precharger circuit 4 becomes non-active. The sense amplifier circuit 5 is activated by the third pulse signal SE outputted from the column controller 13 for thereby sensing and amplifying the data value applied thereto from the data line pair DL,/DL via the precharger circuit 4, and the data amplified in the sense amplifier circuit 5 is externally outputted via the data latch/output buffer circuit 6.
However, as shown in FIG. 3A, in the thusly constituted conventional memory device, the address signals A0.about.An may quickly change their logic values when there occurs noise or a short pulse in the address signals A0.about.An applied from an external system to the address transition detecting sub-circuit 11.
Consequently, the address transition detection sum signal ATDSUM outputted from the address transition detection summing circuit 12 becomes irregular as shown in FIG. 3B. The first pulse signal YE outputted from the column controller 13 also becomes unstable as shown in FIG. 3C, in accordance with the irregular address transition detection sum signal ATDSUM outputted from the address transition detection summing circuit 12. Further, the control signals S0.about.Sn outputted from the column address decoder circuit 2 activated by the first pulse signal YE respectively become unstable.
As shown in FIG. 3D, the voltage difference in data signals outputted in accordance with the unstable control signals S0.about.Sn from a memory cell array via the data line pair DL,/DL becomes insufficient for the sense amplifier circuit 5 to sense, so that the memory device may carry out an erroneous operation during a data read-out operation.